1. Field of the Invention
The present invention relates to a semiconductor device having an insulated gate field effect transistor having a self-align type contact hole, and a fabrication process therefor.
2. Description of the Prior Art
It has still been progressed actively for reducing size and increasing package density of semiconductor elements. In the current technology, ultra high density semiconductor devices such as 1 Gbit dynamic random access memory (GbDRAM) designed under dimensional standard of about 0.18 .mu.m, have been developed and fabricated in experiments. Associating with increasing of package density of the semiconductor device, it has been highly demanded to make a mask alignment margin unnecessary in photolithographic process which is essential process in formation of a semiconductor element structure.
Normally, in fabrication of the semiconductor device, patterns formed of various materials, such as a metal layer, a semiconductor layer, an insulation layer and so forth, are stacked on a semiconductor substrate in a predetermined sequential order to form a semiconductor element of a fine structure. For stacking the patterns for the semiconductor element, it has been required in the photolithographic process to align a mask to a lower layer pattern formed in a preceding process and then to perform patterning an upper layer. However, in the photolithographic process, it is possible to cause offset of position between the upper pattern and the lower pattern. Therefore, it has been required to set a margin within an interval between the patterns anticipating the position offset. However, such margin can be a cause of restriction for increasing of density of the pattern.
Therefore, various technical methods have been studied in order to make the margin unnecessary (marginless structure). It is particularly important to avoid necessity of margin in formation of the contact hole. Such contact hole is frequently formed in various layer on a semiconductor substrate, a semiconductor layer or a metal layer. Therefore, it is most effective for achieving increased package density and increased integration density of the semiconductor device to avoid necessity of the margin. Among a technology for avoiding necessity of the margin, formation process of a self-align type contact hole, as one kind of self-aligning methods, is an effective method. Various studies have been made for concrete processes.
Among formation process of the self-aligning type contact hole, attention has been attracted to a method for forming the contact hole on a diffusion layer in self-alignment with a gate electrode by providing a spacer of an insulation layer in an insulated-gate field-effect transistor, such as a MOS transistor, by anisotropic etching of an insulation layer. One example of such method has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 61-16571.
FIGS. 1A and 1B are illustrations showing a fabrication process of a MOS transistor having above-mentioned known self-align type contact holes, wherein FIG. 1A is a section showing a structure of the semiconductor device and FIG. 1B is a plan view of the semiconductor device.
As shown in FIG. 1A, after formation of a field oxide layer 102 by selectively oxidizing a surface of a silicon substrate 101, a gate oxide layer 104 is formed on the surface of the silicon substrate 101 in a region where the field oxide layer 102 is not formed. Furthermore, an n.sup.+ -polysilicon layer doped with n-type impurity is deposited over the entire surface. Next, after formation of a silicon oxide layer having thickness of approximately 50 nm by oxidizing a surface of the n.sup.+ -polysilicon layer, a silicon nitride layer is deposited in a thickness of approximately 100 nm over the entire surface. Then, a resist pattern defining a gate electrode region and a wiring region is formed. With taking this resist pattern as a mask, etching is performed in the sequential order of the silicon nitride layer, the silicon oxide layer and n.sup.+ -polysilicon layer. Thus, a gate electrode consisting of a gate polysilicon layer 105, a silicon oxide layer 107 and a silicon nitride layer 109 are formed by patterning those three layers. On the other hand, a wiring consisting of a wiring polysilicon layer 106, a silicon oxide layer 108 and a silicon nitride layer 110 are formed by patterning those layers. Subsequently, low concentration impurity is injected in the silicon substrate 101 using the gate electrode and the field oxide layer 102 as a mask by ion implantation.
Next, after removal of the resist pattern, a silicon nitride layer having thickness of approximately 100 nm is deposited over the entire surface. Thereafter, etching is performed by way of reactive ion etching (RIE) method with leaving a side silicon nitride layer 111 on the side surface of the gate polysilicon layer 105, the silicon oxide layer 107 and the silicon nitride layer 109, and a side nitride silicon layer 112 on the side surface of the wiring polysilicon layer 106, the silicon oxide layer 108 and the silicon nitride layer 110. Then, high concentration impurity is injected by way of ion implantation method for forming a source-drain region. The ion implanted region thus obtained has low impurity concentration in the region below the side silicon nitride layer 111, and has high impurity concentration in the region outside of the low impurity concentration region.
Next, an interlayer insulation layer 115 formed of a PSG layer (phosphosilicate glass layer), for example, is deposited over the entire surface. Thereafter, under oxygen or nitrogen atmosphere, heat treatment is performed at about 1000.degree. C. for about 30 minutes. By this heat treatment, the region where ion is implanted is activated to form a source-drain region of LDD structure constituted of a low concentration diffusion region 113 and a high concentration diffusion region 114.
Next, a resist pattern for a contact hole above the diffusion region and a contact hole above the wiring are formed. With taking the resist pattern as a mask, etching is performed for the interlayer insulation layer 115 to form contact holes 116 and 117 on the diffusion region and a contact hole 118 of the wiring layer. At this time, the contact holes 116 and 117 are formed in self-align manner with taking the silicon nitride layer 109 and the side silicon nitride layer 111 as a mask. Next, by forming a resist pattern having greater size than the contact hole in the wiring region, the silicon oxide layer and the silicon nitride layer are etched on the wiring polysilicon layer 106. Then, metal layer patterns 119, 120 and 121 are formed. As a result, as shown in the plan view of FIG. 1B, even when the contact holes 116 and 117 formed on the active region 103 are designed to contact with the gate polysilicon layer 105, the side silicon nitride layer 111 becomes the insulation layer. Therefore, the gate polysilicon layer 105 and the metal layer patterns 119 and 120 will never be electrically shorted.
With such prior art, by covering the upper surface and the side surface of the gate electrode by the silicon nitride layer, the contact hole formed in the diffusion layer to be the source-drain region has no margin relative to the gate electrode to form in self-align manner.
However, in the prior art, thickness of a silicon oxide layer disposed between the lower surface of the side silicon nitride layer 111 formed on the side surface of the gate polysilicon layer 105 and an upper surface of the low concentration diffusion region 113 formed at the surface of the silicon substrate 101, is the same extent to the gate oxide layer 104 or lesser. For example, in the semiconductor device, employing a fine MOS transistor subsequent to 1 GbDRAM which has gate length less than or equal to 0.2 .mu.m, layer thickness of the gate oxide layer becomes less than or equal to approximately 6 nm. Therefore, the layer thickness of the silicon oxide layer below the silicon nitride layer becomes quite thin. As a result, the MOS transistor employing the prior art is degraded in reliability of characteristics, particularly in reliability against hot carrier stress.